29

Rev. 0A | October 2022

www.issi.com - dram@issi.com

IS43/46LR32320C

IS43/46LR16640C

Note :

1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the

clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to

reduce the data rate.

2. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to

VIL(AC) for falling input signals.

3. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions

through the DC region must be monotonic.

4. Input slew rate ≥ 0.5V/ns and < 1.0V/ns.

5. These parameters guarantee device timing but they are not necessarily tested on each device.

6. The transition time for address and command inputs is measured between VIH and VIL.

7. A CK,/CK slew rate must be ≥ 1.0V/ns (2.0V/ns if measured differentially) is assumed for this parameter.

8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific

voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

9. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

10. A maximum of eight Refresh commands can be posted to any given Low-Power DDR SDRAM, meaning that the maximum absolute

interval between any Refresh command and the next Refresh command is 8*tREFI.

11. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system.

It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).

12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or

transitioning from HIGH to LOW at this time, depending on tDQSS.

13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) will degrade accordingly.

14. At least one clock pulse is required during tXP.

15. The specifications in the table for TREF and TREFI are applicable for all temperature grades with TA ≤ +85°C. Only A2 temperature grade

supports operation with TA > +85°C, and these values must be further constrained with TREF max of 32ms, and TREFI max of 3.9μs.

Input setup/hold slew rate [V/ns]

∆tDS/∆tIS [ps]

∆tDH/∆tIH [ps]

1.0

0

0

0.5

+150

+150

CK,/CK setup/hold slew rate [V/ns]

∆tDS/∆tIS [ps]

∆tDH/∆tIH [ps]

1.0

0

0