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Rev. 0A | October 2022

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IS43/46LR32320C

IS43/46LR16640C

Auto Precharge

Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit

command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A

precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or

WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This

device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto

precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an

explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN). The user must not issue another

command to the same bank until the precharge time (tRP) is completed.

Burst Terminate

The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ

command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains

open.

Auto Refresh

AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in

FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the

internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 2Gb Mobile DDR SDRAM

requires AUTO REFRESH cycles at an average interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching

between tasks, some flexibility in the absolute refresh interval is provided.

Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the auto refresh period.

The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.

Self Refresh

The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When

in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an

AUTO REFRESH command except CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during SELF

REFRESH.

During SELF REFRESH, the device is refreshed as identified in the external mode register (see PASR setting). For a the full array refresh, all

four banks are refreshed simultaneously with the refresh frequency set by an internal self refresh oscillator. This oscillator changes due to

the temperature sensors input. As the case temperature of the Mobile DDR SDRAM increases, the oscillation frequency will change to

accommodate the change of temperature. This happens because the DRAM capacitors lose charge faster at higher temperatures. To ensure

efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data.

The procedure for exiting SELF REFRESH requires a sequence of commands. First, Clock must be stable prior to CKE going back HIGH. Once

CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tXSR is required for the completion of any internal refresh in

progress. The SELF REFRESH command is not applicable for operation with TA > 85°C.

Deep Power-down

Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the

devices. Data will not be retained once the device enters Deep Power Down Mode.

This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while

CKE is low. This mode is exited by asserting CKE high.

This mode is not applicable for operation with TA > 85°C.