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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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IS46LR16640C Scheda tecnica(PDF) 28 Page - Integrated Silicon Solution, Inc |
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IS46LR16640C Scheda tecnica(HTML) 28 Page - Integrated Silicon Solution, Inc |
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28 / 47 page  28 Rev. 0A | October 2022 www.issi.com - dram@issi.com IS43/46LR32320C IS43/46LR16640C Parameter Symbol -6 -75 Unit Note Min Max Min Max System Clock Cycle time CL=3 tCK 6 7.5 ns 1 CL=2 12 12 ns 1 DQ Output access time from CK, /CK CL=3 tAC 2.0 5.0 2.5 6.0 ns CL=2 2.0 8.0 2.5 8.0 Clock High pulse width tCH 0.45 0.55 0.45 0.55 tCK Clock Low pulse width tCL 0.45 0.55 0.45 0.55 tCK CKE min. pulse width (High/Low pulse width) tCKE 1 1 tCK DQ and DM Input Setup time tDS 0.6 0.8 ns 2, 3, 4 DQ and DM Input Hold time tDH 0.6 0.8 ns 2, 3, 4 DQ and DM Input Pulse width tDIPW 1.6 1.8 ns 5 Address and Control Input Setup time tIS 1.1 1.3 ns 4, 6, 7 Address and Control Input Hold time tIH 1.1 1.3 ns 4, 6, 7 Address and Control Input Pulse Width tIPW 2.7 3.0 ns 5 DQ & DQS Low-impedance time from CK, /CK tLZ 1.0 1.0 ns 8 DQ & DQS High-impedance time from CK, /CK CL=3 tHZ - 5.0 - 5.5 ns 8 CL=2 - 6.5 - 6.5 DQS - DQ Skew tDQSQ 0.5 0.6 ns 9 Half Clock Period tHP tCH, tCL tCH, tCL ns Data Hold Skew Factor tQHS 0.65 0.75 ns DQ / DQS Output Hold time from DQS tQH tHP-tQHS tHP-tQHS ns Write Command to first DQS Latching Transition tDQSS 0.7 1.25 0.75 1.2 tCK DQS Input High pulse Width tDQSH 0.4 0.6 0.4 0.6 tCK DQS Input Low pulse Width tDQSL 0.4 0.6 0.4 0.6 tCK DQS Falling Edge to CK Setup Time tDSS 0.2 0.2 tCK DQS Falling Edge Hold Time From CK tDSH 0.2 0.2 tCK Access Window of DQS from CK, /CK CL=3 tDQSCK 2.0 5.0 2.5 6.0 ns CL=2 2.0 8.0 2.5 8.0 ns ACTIVE to PRECHARGE Command Period tRAS 42 70K 45 70K ns ACTIVE to ACTIVE Command Period tRC 60 70 ns Mode Register Set command cycle time tMRD 2 2 tCK Average periodic refresh interval tREFI 7.8 7.8 us 10, 15 Auto Refresh Period tRFC 72 72 ns Active to Read or Write delay tRCD 18 22 ns Precharge command period tRP 18 22 ns Active Bank A to Active Bank B Delay tRRD 12 15 ns Read of SRR to next valid command tSRC CL + 1 CL + 1 tCK SRR to read tSRR 2 2 tCK Write Recovery time tWR 15 15 ns Auto Precharge Write Recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) Internal Write to Read Command Delay tWTR 2 2 tCK DQS Read preamble CL=3 tRPRE 0.9 1.1 0.9 1.1 tCK 11 CL=2 0.5 1.1 0.5 1.1 tCK 11 DQS Read postamble tRPST 0.4 0.6 0.4 0.6 tCK DQS Write preamble tWPRE 0.25 0.25 tCK DQS Write preamble setup time tWPRES 0 0 ns 12 DQS Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 13 Exit Power Down to next valid command Delay tXP 1 1 tCK 14 Self Refresh Exit to next valid Command Delay tXSR 120 120 ns Table16: AC Characteristic (AC operation conditions unless otherwise noted) |
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