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Rev. 0A | October 2022

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IS43/46LR32320C

IS43/46LR16640C

Clock Stop Mode

Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption during idle periods of

the device.

Conditions: the Mobile DDR SDRAM supports clock stop in case:

• The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion,

including any data-out during read bursts; the number of required clock pulses per access command depends on the device's AC timing

parameters and the clock frequency;

• The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;

• CKE is held HIGH.

When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with CK held

LOW and /CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command have to be issued for at least one clock

cycle before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics.

Figure37 illustrates the clock stop mode:

• Initially the device is in clock stop mode;

• The clock is restarted with the rising edge of T0 and a NOP on the command inputs;

• With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this

access command has completed;

• T

n is the last clock pulse required by the access command latched with T1.

• The timing condition of this access command is met with the completion of T

n; therefore Tn is the last clock pulse required by this

command and the clock is then stopped.

Figure 37 : Clock Stop Mode

DQ,DQS

(High – Z)

Exit Clock

Stop Mode

Enter Clock

Stop Mode

Vail

Command

CKE

T0

T1

T2

T

n

/CLK

CLK

ADD

Timing Condition

CMD

Clock

stopped

Don’t Care

NOP

CMD

NOP

NOP

NOP

Valide

High