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IS46LR16640C Scheda tecnica(PDF) 26 Page - Integrated Silicon Solution, Inc |
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IS46LR16640C Scheda tecnica(HTML) 26 Page - Integrated Silicon Solution, Inc |
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26 / 47 page ![]() 26 Rev. 0A | October 2022 www.issi.com - dram@issi.com IS43/46LR32320C IS43/46LR16640C Table15B : DC Characteristic (DC operating conditions unless otherwise noted) Note : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. -75 is for reference only. Parameter Symbol Test Condition Speed Unit Note -5 -6 -75 Operating one bank active- precharge current IDD0 tRC = tRC(min), tCK = tCK(min), CKE is HIGH, /CS is HIGH between valid commands, address inputs are SWITCHING, data bus inputs are STABLE 95 90 85 mA 1 Precharge power-down standby current IDD2P All banks idle, CKE is LOW, /CS is HIGH, tCK = tCK(min), address and control inputs are SWITCHING, data bus inputs are STABLE 10 mA Precharge power-down standby current with clock stop IDD2PS All banks idle, CKE is LOW, /CS is HIGH, CK = LOW, /CK = HIGH, address and control inputs are SWITCHING, data bus inputs are STABLE 10 mA Precharge non power-down standby current IDD2N All banks idle, CKE is HIGH, /CS is HIGH, tCK = tCK(min) , address and control inputs are SWITCHING, data bus inputs are STABLE 70 mA Precharge non power-down standby current with clock stop IDD2NS All banks idle, CKE is HIGH, /CS is HIGH, CK = LOW, /CK = HIGH, address and control inputs are SWITCHING, data bus inputs are STABLE 60 mA Active power-down standby current IDD3P One bank active, CKE is LOW, /CS is HIGH, tCK = tCK(min), address and control inputs are SWITCHING, data bus inputs are STABLE 10 mA Active power-down standby current with clock stop IDD3PS One bank active, CKE is LOW, /CS is HIGH, CK = LOW, /CK = HIGH, address and control inputs are SWITCHING, data bus inputs are STABLE 10 mA Active non power-down standby current IDD3N One bank active, CKE is HIGH, /CS is HIGH, tCK = tCK(min), address and control inputs are SWITCHING, data bus inputs are STABLE 70 mA Active non power-down standby current with clock stop IDD3NS One bank active, CKE is HIGH, /CS is HIGH, CK = LOW, /CK = HIGH, address and control inputs are SWITCHING, data bus inputs are STABLE 54 mA Operating burst read current IDD4R One bank active, BL=4, CL=3, tCK = tCK(min), continuous read bursts, IOUT=0mA, address inputs are SWITCHING, 50% data change each burst transfer 135 130 125 mA 1 Operating burst write current IDD4W One bank active, BL=4, tCK=tCK(min), continuous write bursts, address inputs are SWITCHING, 50% data change each burst transfer 135 130 125 mA 1 Auto Refresh Current IDD5 tRC=138ns, tCK=tCK(min), burst refresh, CKE is HIGH, address and control inputs are SWITCHING, data bus inputs are STABLE 160 mA 2 Self Refresh Current PASR TCSR IDD6 CKE is LOW CK=LOW, /CK=HIGH tCK=tCK(min) Extended Mode Register set to all 0's, address and control inputs are STABLE, data bus inputs are STABLE mA 4 4 banks 85°C 6.5 45°C 2.3 2 Banks 85°C 4.5 45°C 5.9 1 Bank 85°C 5.2 45°C 1.8 Half Bank 85°C 4.6 45°C 1.6 Quarter Bank 85°C 4.6 45°C 1.6 Standby Current in Deep Power Down Mode IDD8 Address and control inputs are STABLE, data bus inputs are STABLE 80 uA 5 4. Values apply for tA ≤ 85oC 5. Typical value at room temperature. |
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