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CDCE72010 Scheda tecnica(PDF) 32 Page - Texas Instruments

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Il numero della parte CDCE72010
Spiegazioni elettronici  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

CDCE72010 Scheda tecnica(HTML) 32 Page - Texas Instruments

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CDCE72010
SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com
Register 11: SPI Mode
SPI
RAM
RELATED
POWER UP
BIT NAME
DESCRIPTION/FUNCTION
BIT
BIT
BLOCK
CONDITION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
1
4
0
PRI_DIV2
Input Buffers
If set to 1 enables Primary Reference Divide by 2
EEPROM
5
1
SEC_DIV2
Input Buffers
If set to 1 enables Secondary Reference Divide by 2
EEPROM
FB Path Integer
When set to 0, FB divider is active
6
2
FB_DIS
EEPROM
Counter 32
When set to 1, FB divider is disabled
FB Path Integer
When set to 0, FB clock is CMOS type
7
3
FB_CML_SEL
EEPROM
Counter 32
When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL
FB-Divider/
When set to 0, Input clock for FB not inverted (normal mode, low speed)
8
4
FB_INCLK_INV
Deterministic
EEPROM
When set to 1, Input clock for FB inverted (higher speed mode)
Blocks
9
5
FB_COUNT32_0
Feedback Counter Bit0
10
6
FB_COUNT32_1
Feedback Counter Bit1
11
7
FB_COUNT32_2
Feedback Counter Bit2
FB Path Integer
12
8
FB_COUNT32_3
Feedback Counter Bit3
EEPROM
Counter 32
13
9
FB_COUNT32_4
Feedback Counter Bit4
14
10
FB_COUNT32_5
Feedback Counter Bit5
15
11
FB_COUNT32_6
Feedback Counter Bit6
16
12
FB_PHASE0
Feedback Phase Adjust Bit0
17
13
FB_PHASE1
Feedback Phase Adjust Bit1
18
14
FB_PHASE2
Feedback Phase Adjust Bit2
FB Path Integer
19
15
FB_PHASE3
Feedback Phase Adjust Bit3
EEPROM
Counter 32
20
16
FB_PHASE4
Feedback Phase Adjust Bit4
21
17
FB_PHASE5
Feedback Phase Adjust Bit5
22
18
FB_PHASE6
Feedback Phase Adjust Bit6
If set to 0, PLL is in normal mode
23
19
PD_PLL
PLL
EEPROM
If set to 1, PLL is powered down
When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div and
Clock Tree and
FB_MUX_SEL
Det
24
20
Deterministic
EEPROM
See Table 6
When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div and
Block
Det
OUT_MUX_SEL
25
21
Clock Tree
If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock
EEPROM
See Table 6
Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)
26
22
FB_SEL
Diagnostics
EEPROM
The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)
27
23
NRESHAPE1
Reshapes the Reference Clock Signal 0, Disable Reshape 1
EEPROM
Reference
If set to 0 it enables short delay for fast operation
Selection Control
28
24
SEL_DEL1
EEPROM
If Set to 1 Long Delay recommended for Input References below 150Mhz
29
25
RESET_HOLD
Reset Circuitry
If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET
EEPROM
30
26
EPUNLOCK
Status
EEPROM Unlock
EEPROM
31
27
EPSTATUS
Status
EEPROM Status
EEPROM
Table 6. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection
FB_MUX_SEL
OUT_MUX_SEL
PLL FEED AND OUTPUTS FEED
AUX INPUT OR OUTPUT 9
0
0
VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block
OUTPUT 9 is enabled
1
0
AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block
AUX IN is enabled
0
1
VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is enabled
1
1
AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is enabled
32
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