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CDCE72010 Scheda tecnica(PDF) 33 Page - Texas Instruments

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Il numero della parte CDCE72010
Spiegazioni elettronici  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

CDCE72010 Scheda tecnica(HTML) 33 Page - Texas Instruments

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CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 12: SPI Mode (RAM only Register)
SPI
RAM
RELATED
POR
BIT NAME
DESCRIPTION/FUNCTION
BIT
BIT
BLOCK
DEFAULT
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
1
4
0
RESERVED
RAM
5
1
RESERVED
RAM
6
2
RESERVED
RAM
7
3
RESERVED
RAM
Status
8
4
INDET_AUX
It indicates that a clock is present at AUX-input (Y9) , when set to 1
RAM
(Read Only)
Status
9
5
INDET_VCXO
It indicates that a clock is present at VCXO-input , when set to 1
RAM
(Read Only)
Status
10
6
PLL_LOCK
It indicates that the PLL is locked when set to 1
RAM
(Read Only)
11
7
PD
Power Down
Power-down mode on when set to 0, Off when set to 1
1
RAM
If set to 0 this bit forces “RESET or HOLD” depending on the setting of
RESET or
12
8
Reset
RESET_HOLD bit in Register 11. If set to 0 RESET or HOLD are asserted.
1
RAM
HOLD
Set for 1 for normal operation.
General Test Mode Enable, Test Mode is only enabled, if this bit is set to 1
13
9
GTME
Diagnostics
0
RAM
This bit controls many test modes on the device.
14
10
REVISION0
Status
Read only: Revision Control Bit 0
RAM
15
11
REVISION1
Status
Read only: Revision Control Bit 1
RAM
16
12
REVISION2
Status
Read only: Revision Control Bit 2
RAM
When set to 0, all blocks are on. (TI Test-GTME)
When set to 1, the VCXO Input, AUX Input and all output buffers and divider
17
13
PD_IO
Diagnostics
0
RAM
blocks are disabled. This test is done to measure the effect of the I/O circuitry
on the Charge Pump. (TI Test-GTME)
If set to 0 that Status pin is used as CMOS output to enable TI test modes.
18
14
SXOIREF
Diagnostics
Set to 1 when IREFRES is set to 1 and 12-K
Ω resistor is connected. (TI
0
RAM
Test-GTME)
19
15
SHOLD
Diagnostics
Routes the HOLD signal to the PLL_LOCK pin when set to 1 (TI Test-GTME)
0
RAM
20
16
RESERVED
0
RAM
21
17
STATUS0
TI test registers. For TI use only
22
18
STATUS1
Route internal signals to external STATUS pin.
Diagnostics
1
RAM
STATUS3, STATUS2, STATUS1, STATUS0 (S3, S2, S1, S0) will select that
23
19
STATUS2
internal status signal that will be routed to the external STATUS pin.
24
20
STATUS3
25
21
TITSTCFG0
Diagnostics
TI test registers. For TI use only
0
RAM
26
22
TITSTCFG1
Diagnostics
TI test registers. For TI use only
0
RAM
27
23
TITSTCFG2
Diagnostics
TI test registers. For TI use only
0
RAM
28
24
TITSTCFG3
Diagnostics
TI test registers. For TI use only
0
RAM
29
25
PRIACTIVITY
Status
It indicates activity on the Primary when set to - (read only bit)
RAM
30
26
SECACTIVITY
Status
It indicates activity on the Secondary when set to - (read only bit)
RAM
31
27
RESERVED
RAM
NOTE:
If TI test bits (Register 12< RAM bits 17,18,19, 20> are set to 1000, Reference Select
from the Smart Mux will show on the STATUS pin ( Low = Primary REF is selected
and High = Secondary REF is selected).
Copyright © 2008, Texas Instruments Incorporated
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