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CDCE72010 Scheda tecnica(PDF) 41 Page - Texas Instruments

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Il numero della parte CDCE72010
Spiegazioni elettronici  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

CDCE72010 Scheda tecnica(HTML) 41 Page - Texas Instruments

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CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 5: CD Mode
SPI
RAM
RELATED
POWER UP
BIT NAME
DESCRIPTION/FUNCTION
BIT
BIT
BLOCK
CONDITION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
4
0
BIAS_DIV45<0>
When BIAS_DIV45<1:0> =
Output Divider
00, No current reduction for all output-divider
EEPROM
4 and 5
01, Current reduction for all output-divider by about 20%
5
1
BIAS_DIV45<1>
10, Current reduction for all output-divider by about 30%
6
2
BIAS_DIV67<0>
When BIAS_DIV67<1:0> =
Output Divider
00, No current reduction for all output-divider
EEPROM
6 and 7
01, Current reduction for all output-divider by about 20%
7
3
BIAS_DIV67<1>
10, Current reduction for all output-divider by about 30%
8
4
RESERVED
EEPROM
9
5
RESERVED
EEPROM
10
6
PH5ADJC0
11
7
PH5ADJC1
12
8
PH5ADJC2
13
9
PH5ADJC3
Output 5
Coarse phase adjust select for output divider 5
EEPROM
14
10
PH5ADJC4
15
11
PH5ADJC5
16
12
PH5ADJC6
17
13
OUT5DIVRSEL0
18
14
OUT5DIVRSEL1
19
15
OUT5DIVRSEL2
OUTPUT DIVIDER 5 Ratio Select
20
16
OUT5DIVRSEL3
Output 5
EEPROM
(See Table 7)
21
17
OUT5DIVRSEL4
22
18
OUT5DIVRSEL5
23
19
OUT5DIVRSEL6
When set to 0, the divider is disabled
24
20
EN5DIV
Output 5
EEPROM
When set to 1, the divider is enabled
25
21
PECL5HISWING
Output 5
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
CD1 PIN is high and DIVPHA5CD1H is set to low
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5
26
22
DIVPHA5CD1H
CD1 High
EEPROM
CD1 PIN is high and DIVPHA5CD1H is set to high
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
CD1 PIN is low and DIVPHA5CD1L is set to low
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5
27
23
DIVPHA5CD1L
CD1 Low
EEPROM
CD1 PIN is low and DIVPHA5CD1L is set to high
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
28
24
OUTBUF5CD2LX
Output Buffer 5 Signaling Selection when CD2 in low
CD2 Low
EEPROM
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
29
25
OUTBUF5CD2LY
30
26
OUTBUF5CD2HX
Output Buffer 5 Signaling Selection when CD2 in high
CD2 High
EEPROM
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
31
27
OUTBUF5CD2HY
Copyright © 2008, Texas Instruments Incorporated
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