CDCE72010 datasheet(21/70 Pages) TI

21 / 70 page

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

SPI

RAM

POWER UP

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

BIT

Bit

CONDITION

Address 0

Address 1

Address 2

Address 3

INBUFSELX

Reference Input

Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)

EEPROM

Buffers

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin

INBUFSELY

PRISEL

When REFSELCNTRL is set to 1, the following settings apply:

If RAM Bits (2,3): 00 – No input buffer is selected/active

Reference Input

If RAM Bits (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down

EEPROM

Buffer

SECSEL

If RAM Bits (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down

If RAM Bits (2,3): 11 – Auto Select (PRI then SEC).

When set to 0, PRI- or SEC-clock is selected, depending on bits 2 and 3

Divider START

VCXOSEL

(default)

EEPROM

DETERM-Block

When set to 1, VCXO/AUX-clock is selected, overwrites bits 2 and 3

Reference Select Control to select if the control of the reference is from the

internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.

- When set to 0: the external pin REF_SEL takes over the selection between

Reference

PRI and SEC. Autoselect is not available.

REFSELCNTRL

Selection

EEPROM

- When set to 1: The external pin REF_SEL is ignored. The table in (Register 0

Control

<2 and 3> ) describes which reference input clock is selected and available

(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing

diagram.

DELAY_PFD0

PFD pulse width PFD bit 0

PFD

EEPROM

PFD pulse width PFD bit 1

DELAY_PFD1

CP_MODE

Selects 3V option [0] or 5V option [1]

EEPROM

Charge Pump

Determines which direction CP current will regulate (Reference Clock leads to

CP_DIR

EEPROM

Feedback Clock, Positive CP output current [0], Negative CP output current [1])

Switches the current source in the charge pump on when set to 1 (TI

CP_SRC

EEPROM

Test-GTME)

Charge Pump

CP_SNK

Diagnostics

Switches the current sink in the charge pump on when set to 1 (TI Test-GTME)

EEPROM

CP_OPA

Switches the charge pump op-amp off when set to 1 (TI Test-GTME)

EEPROM

CP_PRE

Preset charge pump output voltage to VCC_CP/2, on [1], off [0]

EEPROM

ICP0

CP current setting bit 0

EEPROM

ICP1

Charge Pump

CP current setting bit 1

EEPROM

ICP2

CP current setting bit 2

EEPROM

ICP3

CP current setting bit 3

EEPROM

RESERVED

EEPROM

RESERVED

EEPROM

Charge Pump

Enables the 12-k

Ω pull-down resistor at I_REF_CP pin when set to 1 (TI

IREFRES

EEPROM

Diagnostics

Test-GTME)

PECL0HISWING

Output 0

High output voltage swing in LVPECL mode if set to 1

EEPROM

CMOSMODE0PX

LVCMOS mode select for OUTPUT 0 positive pin.

Output 0

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE0PY

CMOSMODE0NX

LVCMOS mode select for OUTPUT 0 negative pin.

Output 0

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE0NY

RAM BITS

OUTPUT TYPE

OUTBUFSEL0X

Output 0

EEPROM

LVPECL

LVDS

OUTBUFSEL0Y

Output 0

LVCMOS

See Settings Above(1)

EEPROM

All Outputs Disabled

(1)

Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.

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