CDCE72010 datasheet(57/70 Pages) TI

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ANALOG LOCK DETECT

160kW

5pF

110µA

(Lock)

Out

=1/C*I*t

Out

=0.55V

high

=0.35V

low

Example:

forI=110µA,C=10n,V

=3.3Vand

=0.55*V

=1.8V

=>t=164µs

high

Out

Power_Down

110µA

(Out-of-Lock)

Lock_Out

Lock_In

PLL_LOCK

(Output)

FREQUENCY HOLD-OVER MODE

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110

µA

current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but

jittering of PLL_LOCK will be suppressed like possible in case of digital lock. The time PLL_LOCK needs to

return to out of lock depends on the level of VOUT, when the current source starts to unload the external

capacitor.

Figure 23. Analog Lock

The HOLD-Function is a CDCE72010 feature that helps to improve system reliability. The HOLD-Function holds

the output frequency in case the input reference clock fails or is disrupted. During HOLD, the Charge-Pump is

switched off (3-State) freezing the last valid output frequency. The Hold-Function will be released after a valid

reference clock is reapplied to the clock input and detected by the CDCE72010. For proper HOLD function, the

Analog PLL-Lock-Detect mode has to be active. The following settings are involved with the HOLD Function:

• Lock Detect Window: Defines the window in ns inwhich the Lock is valid. The size is 3.5ns, 8.5ns, 18.5ns.

Lock is set if Reference Clock and Feedback Clock are inside this predefined Lock-Detect Window for a

pre-selected number of successive cycles.

• Out-of-Lock: Defines the out-of-lock condition: If the Reference Clock and the Feedback Clock at the PFD are

outside the predefined Lock Detect Window.

• Number of Clock Cycles: Defines the number of successive PFD cycles which have to occur inside the lock

window to set Lock detect. This does not apply for Out-of-Lock condition.

• Hold-Function: Selects HOLD-Function (see more details below).

• Hold-Trigger: Defines whether the HOLD-Function is always activated or whether it is dependent on the state

of the analog PLL Lock detect output. In the latter case, HOLD is activated if Lock is set (high) and

de-activated if Lock is reset (low).

• Analog PLL Lock Detect: Analog Lock output charges or discharges an external capacitor with every valid

Lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCE72010 supports two types of HOLD functions, one external controllable HOLD mode and one internal

mode, HOLD.

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