CDCE72010 datasheet(31/70 Pages) TI

31 / 70 page

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

SPI

RAM

POWER UP

BIT NAME

DESCRIPTION/FUNCTION

BIT

BLOCK

CONDITION

Address 0

Address 1

Address 2

Address 3

Reference Divider M Bit 0

Reference Divider M Bit 1

Reference Divider M Bit 2

Reference Divider M Bit 3

Reference Divider M Bit 4

Reference Divider M Bit 5

Reference

Reference Divider M Bit 6

(PRI/SEC) Divider

EEPROM

Reference Divider M Bit 7

Reference Divider M Bit 8

Reference Divider M Bit 9

M10

Reference Divider M Bit 10

M11

Reference Divider M Bit 11

M12

Reference Divider M Bit 12

M13

Reference Divider M Bit 13

VCXO Divider N Bit 0

VCXO Divider N Bit 1

VCXO Divider N Bit 2

VCXO Divider N Bit 3

VCXO Divider N Bit 4

VCXO Divider N Bit 5

VCXO Divider N Bit 6

VCXO/AUX/SEC

EEPROM

Divider N

VCXO Divider N Bit 7

VCXO Divider N Bit 8

VCXO Divider N Bit 9

N10

VCXO Divider N Bit 10

N11

VCXO Divider N Bit 11

N12

VCXO Divider N Bit 12

N13

VCXO Divider N Bit 13

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