H8SSLASH2214 datasheet(336/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 276 of 872

REJ09B0189-0400

Table 8.9

Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM

On-Chip I/O

Registers

External Devices

Bus width

Access states

Vector read

—

6 + 2 m

3 + m

Execution

status

information

read/write

—

Byte data read

3 + m

Word data read

6 + 2 m

3 + m

Byte data write

3 + m

Word data write

6 + 2 m

3 + m

Internal operation S

m: Number of wait states in external device access

The number of execution states is calculated from the formula below. Note that

Σ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · S

I + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

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