H8SSLASH2214 datasheet(370/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 310 of 872

REJ09B0189-0400

(2) Port 7 Data Register (P7DR)

P77DR

R/W

P76DR

R/W

P75DR

R/W

P74DR

R/W

P73DR

R/W

P70DR

R/W

P72DR

R/W

P71DR

R/W

Bit

Initial value :

R/W

P7DR is an 8-bit readable/writable register that stores output data for the port 7 pins (P77 to P70).

P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port 7 Register (PORT7)

P77

—*

P76

—*

P75

—*

P74

—*

P73

—*

P70

—*

P72

—*

P71

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins P77 to P70.

PORT7 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port 7 pins (P77 to P70) must always be performed on P7DR.

If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7

read is performed while P7DDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORT7 contents are determined by the pin

states, as P7DDR and P7DR are initialized. PORT7 retains its previous state after a manual reset

and in software standby mode.

(4) External Module Connection Output Pin Select Register (OPINSEL)

Bit

—

P76

STPOE

P75

MSOE

P74

DTCOE

—

Initial value : Undefined

Undefined Undefined Undefined Undefined

R/W

—

R/W

—

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