H8SSLASH2214 datasheet(376/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 316 of 872

REJ09B0189-0400

9.7.2

Table 9.10 shows the port A register configuration.

Table 9.10

Port A Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port A data direction register

PADDR

H'0

H'FE39

Port A data register

PADR

R/W

H'0

H'FF09

Port A register

PORTA

Undefined

H'FFB9

Port A MOS pull-up control register

PAPCR

R/W

H'0

H'FE40

Port A open-drain control register

PAODR

R/W

H'0

H'FE47

Notes: 1. Lower 16 bits of the address.

2. Value of bits 3 to 0.

(1) Port A Data Direction Register (PADDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3DDR

PA0DDR

PA2DDR

PA1DDR

Bit

Initial value :

R/W

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A. PADDR cannot be read; if it is, an undefined value will be read.

Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.

Since this register is a write-only register, do not use bit manipulation instructions to write to this

PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It

retains its previous state after a manual reset and in software standby mode. The OPE bit in

SBYCR is used to select whether the address output pins retain their output state or become high-

impedance when a transition is made to software standby mode.

(a) Modes 4 to 6

If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port

A pins are address outputs.

When address output is disabled, setting a PADDR bit to 1 makes the corresponding port A pin

an output port, while clearing the bit to 0 makes the pin an input port.

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