H8SSLASH2214 datasheet(377/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 317 of 872

REJ09B0189-0400

(b) Mode 7

Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing

the bit to 0 makes the pin an input port.

(2) Port A Data Register (PADR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3DR

R/W

PA0DR

R/W

PA2DR

R/W

PA1DR

R/W

Bit

Initial value :

R/W

PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to

PA0).

Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.

PADR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It

retains its previous state after a manual reset and in software standby mode.

(3) Port A Register (PORTA)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3

—*

PA0

—*

PA2

—*

PA1

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins PA3 to PA0.

PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port A pins (PA3 to PA0) must always be performed on PADR.

Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.

If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A

read is performed while PADDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin

states, as PADDR and PADR are initialized. PORTA retains its previous state after a manual reset

and in software standby mode.

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