H8SSLASH2214 datasheet(383/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 323 of 872

REJ09B0189-0400

9.8.2

Table 9.13 shows the port B register configuration.

Table 9.13

Port B Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port B data direction register

PBDDR

H'00

H'FE3A

Port B data register

PBDR

R/W

H'00

H'FF0A

Port B register

PORTB

Undefined

H'FFBA

Port B MOS pull-up control register

PBPCR

R/W

H'00

H'FE41

Note: * Lower 16 bits of the address.

(1) Port B Data Direction Register (PBDDR)

PB7DDR

PB6DDR

PB5DDR

PB4DDR

PB3DDR

PB0DDR

PB2DDR

PB1DDR

Bit

Initial value :

R/W

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.

Since this register is a write-only register, do not use bit manipulation instructions to write to this

PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode. The OPE bit in SBYCR is used

to select whether the address output pins retain their output state or become high-impedance when

a transition is made to software standby mode.

(a) Modes 4 to 6

If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port

B pins are address outputs.

When address output is disabled, setting a PBDDR bit to 1 makes the corresponding port B pin

an output port, while clearing the bit to 0 makes the pin an input port.

(b) Mode 7

Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing

the bit to 0 makes the pin an input port.

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