H8SSLASH2214 datasheet(430/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 370 of 872

REJ09B0189-0400

10.2.2

Timer Mode Register (TMDR)

—

BFB

R/W

BFA

R/W

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 0: TMDR0

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 1: TMDR1

Channel 2: TMDR2

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1 and 2 which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be

modified.

Bit 5

BFB

Description

TGRB operates normally

(Initial value)

TGRB and TGRD used together for buffer operation

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