H8SSLASH2214 datasheet(440/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 380 of 872

REJ09B0189-0400

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by

the TCFV flag when the TCFV flag in TSR is set to 1.

Bit 4

TCIEV

Description

Interrupt requests (TCIV) by TCFV disabled

(Initial value)

Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channel 0.

In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGIED

Description

Interrupt requests (TGID) by TGFD bit disabled

(Initial value)

Interrupt requests (TGID) by TGFD bit enabled

Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the

TGFC bit when the TGFC bit in TSR is set to 1 in channel 0.

In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.

Bit 2

TGIEC

Description

Interrupt requests (TGIC) by TGFC bit disabled

(Initial value)

Interrupt requests (TGIC) by TGFC bit enabled

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the

TGFB bit when the TGFB bit in TSR is set to 1.

Bit 1

TGIEB

Description

Interrupt requests (TGIB) by TGFB bit disabled

(Initial value)

Interrupt requests (TGIB) by TGFB bit enabled

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