H8SSLASH2214 datasheet(511/936 Pages) RENESAS

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Section 11 Watchdog Timer (WDT)

Rev.4.00 Sep. 18, 2008 Page 451 of 872

REJ09B0189-0400

11.5.3

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, errors could occur in the incrementation. Software must stop the watchdog timer (by

clearing the TME bit to 0) before switching the mode.

11.5.4

Internal Reset in Watchdog Timer Mode

If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally if

TCNT overflows, but TCNT and TCSR in WDT will be reset.

TCNT, TCSR, and RSTCR cannot be written to for a 132-state interval after overflow occurs, and

a read of the WOVF flag is not recognized during this time. It is therefore necessary to wait for

132 states after overflow occurs before writing 0 to the WOVF flag to clear it.

11.5.5

OVF Flag Clear Operation in Interval Timer Mode

In interval timer mode, if a contention between an OVF flag set and an OVF flag read occurs,

there are cases where even though the OVF = 1 state was read, the flag is not cleared when it is set

to 0. In cases such as when the interval timer interrupt is disabled and the OVF flag is polled, that

is, in cases where contention between an OVF flag set and an OVF flag read may occur, the

application should read the OVF = 1 state at least twice and then set OVF to 0.

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