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H8S/2214 Scheda tecnica(PDF) 515 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 515 Page - Renesas Technology Corp |
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515 / 936 page ![]() Section 12 Serial Communication Interface (SCI) Rev.4.00 Sep. 18, 2008 Page 455 of 872 REJ09B0189-0400 12.1.2 Block Diagram Figures 12.1 and 12.2 show block diagrams of the SCI. Parity generation Parity check Transmit/ receive control Baud rate generator Clock External clock Average transfer rate generator at 10.667 MHz • 115.152 kbps • 460.606 kbps at 16 MHz • 115.192 kbps • 460.784 kbps • 720 kbps Internal data bus RxD0 RDR TDR RSR TSR SCMR SSR SCR SMR SEMR BRR φ φ/4 φ/16 φ/64 TEI TxI RxI ERI SCK0 C/ A CKE1 SSE RSR: RDR: TSR: TDR: SMR: Legend: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCR: SSR: SCMR: BRR: SEMR: Serial control register Serial status register Serial card mode register Bit rate register Serial extended mode register TxD0 PG1/ IRQ7 SCI0 Module data bus TPU TIOCA1 TIOCA2 TCLKA Figure 12.1 Block Diagram of SCI0 |
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