H8SSLASH2214 datasheet(541/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 481 of 872

REJ09B0189-0400

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV

bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the

E bit in SMR.

Bit 2

SINV

Description

TDR contents are transmitted without modification

(Initial value)

Receive data is stored in RDR without modification

TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.

12.2.10

Serial Extended Mode Register 0 (SEMR0)

SSE

R/W

—

Undefined

—

Undefined

—

Undefined

—

ABCS

R/W

ACS0

R/W

ACS2

R/W

ACS1

R/W

Bit

Initial value

R/W

SEMR0 is an 8-bit register that extends the functions of SCI0.

SEMR0 enables selection of the SCI0 select function in synchronous mode, base clock setting in

asynchronous mode, and also clock source selection and automatic transfer rate setting.

SEMR0 is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state

in module stop mode and software standby mode.

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