H8SSLASH2214 datasheet(542/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 482 of 872

REJ09B0189-0400

Bit 7—SCI0 Select Enable (SSE): Allows selection of the SCI0 select function when an external

clock is input in synchronous mode. When the SCI0 select function is enabled, if 1 is input to the

PG1/IRQ7 pin, TxD0 output goes to the high-impedance state, SCK0 input is fixed high inside the

chip, and SCI0 data transmission/reception is halted.

The SSE setting is valid when external clock input is used (CKE1 = 1 in SCR) in synchronous

mode (C/

A = 1 in SMR). When an internal clock is selected (CKE1 = 0 in SCR) in synchronous

mode, or when the chip is in asynchronous mode (C/

A = 0 in SMR), the SCI0 select function is

disabled even if SSE is set to 1.

Bit 7

SSE

Description

SCI0 select function disabled

(Initial value)

SCI0 select function enabled

When PG1/IRQ7 pin input = 1, TxD0 output goes to high-impedance state and SCK0

clock input is fixed high

Bits 6 to 4—Reserved: Write 0 to these bits.

Bit 3—Asynchronous Base Clock Select (ABCS): Selects the 1-bit-interval base clock in

asynchronous mode.

The ABCS setting is valid in asynchronous mode (C/

A = 0 in SMR). It is invalid in synchronous

mode (C/

A = 1 in SMR).

Bit 3

ABCS

Description

SCI0 operates on base clock with frequency of 16 times transfer rate

(Initial value)

SCI0 operates on base clock with frequency of 8 times transfer rate

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