H8SSLASH2214 datasheet(552/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 492 of 872

REJ09B0189-0400

(2) Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/

A bit in

SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table

12.9.

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate

used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 12.6.

1 frame

0/1

Figure 12.6 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode)

(3) Data Transfer Operations

(a) SCI initialization (asynchronous mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then

initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to

0 before making the change using the following procedure. When the TE bit is cleared to 0, the

TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the

contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

When an external clock is used the clock should not be stopped during operation, including

initialization, since operation is uncertain.

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