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H8S/2214 Scheda tecnica(PDF) 557 Page - Renesas Technology Corp

Il numero della parte H8S/2214
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  936 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2214 Scheda tecnica(HTML) 557 Page - Renesas Technology Corp

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Section 12 Serial Communication Interface (SCI)
Rev.4.00 Sep. 18, 2008 Page 497 of 872
REJ09B0189-0400
(c) Serial data reception (asynchronous mode)
Figures 12.10 and 12.11 show a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR
[4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER
∨ FER ∨ ORER = 1
RDRF = 1
All data received?
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Receive error processing and
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
all cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when DMAC or DTC* is
activated by an RXI interrupt and
the RDR value is read.
Note: * The RDRF flag is cleared automatically by DTC
only when the DTC DISEL bit is 0 and
furthermore the transfer counter is not 0.
Therefore the CPU must clear the RDRF flag
when either DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is 0.
[1]
[2] [3]
[4]
[5]
Figure 12.10 Sample Serial Reception Data Flowchart (1)



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