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H8S/2214 Scheda tecnica(PDF) 561 Page - Renesas Technology Corp

Il numero della parte H8S/2214
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  936 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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H8S/2214 Scheda tecnica(HTML) 561 Page - Renesas Technology Corp

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Section 12 Serial Communication Interface (SCI)
Rev.4.00 Sep. 18, 2008 Page 501 of 872
REJ09B0189-0400
12.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 12.13 shows an example of inter-processor communication using the multiprocessor
format.
(1) Data Transfer Format
There are four data transfer formats.
When the multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 12.11.
(2) Clock
See the section on asynchronous mode.



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