H8SSLASH2214 datasheet(615/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 555 of 872

REJ09B0189-0400

15.6

The registers used to control the on-chip flash memory when enabled are shown in table 15.5.

In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER,

SCRX).

Table 15.5

Abbreviation

R/W

Initial Value

Address*

Flash memory control register 1

FLMCR1*

R/W*

H'00*

H'FFA8

Flash memory control register 2

FLMCR2*

H'00

H'FFA9

Erase block register 1

EBR1*

R/W*

H'00*

H'FFAA

Erase block register 2

EBR2*

R/W*

H'00*

H'FFAB

RAM emulation register

RAMER*

R/W

H'00

H'FEDB

Serial control register X

SCRX

R/W

H'00

H'FDB4

Notes: 1. Lower 16 bits of the address.

2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if

FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is

disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the

FWE bit in FLMCR1 is not set to 1.

3. When a high level is input to the FWE pin, the initial value is H'80.

4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in

FLMCR1 is not set, these registers are initialized to H'00.

5. FLMCR1, FLMCR2, EBR1, EBR2, and RAMER are 8-bit registers.

Only byte access can be used on these registers, with the access requiring two states.

These registers are for use exclusively by the flash memory version. Reads to the

corresponding addresses in the masked ROM version will return an undefined value,

and writes to these addresses are invalid.

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