H8SSLASH2214 datasheet(672/936 Pages) RENESAS

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Section 16 Clock Pulse Generator

Rev.4.00 Sep. 18, 2008 Page 612 of 872

REJ09B0189-0400

Table 16.4

External Clock Input Conditions

Item

Symbol

Min.

Max.

Unit

Test Conditions

External clock input lowpulse width

EXL

—

Figure 16.6

External clock input high pulse width

EXH

—

External clock rise time

EXr

—

6.25

External clock fall time

EXf

—

6.25

Clock low pulse width level

0.4

0.6

cyc

φ ≥ 5 MHz Figure 18.3

—

φ < 5 MHz

Clock high pulse width level

0.4

0.6

cyc

φ ≥ 5 MHz

—

φ < 5 MHz

The external clock input conditions when the duty adjustment circuit is not used are shown in

table 16.5 and figure 16.6. When the duty adjustment circuit is not used, the

φ output waveform

depends on the external clock input waveform, and so no restrictions apply.

Table 16.5

External Clock Input Conditions when the Duty Adjustment Circuit Is not Used

Item

Symbol

Min.

Max.

Unit

Test Conditions

External clock input low pulse width

EXL

31.25

—

Figure 16.6

External clock input high pulse width

EXH

31.25

—

External clock rise time

EXr

—

6.25

External clock fall time

EXf

—

6.25

Note:

When duty adjustment circuit is not used, the maximum frequency decreases according to

the input waveform. (Example: When t

EXL = tEXH = 50 ns, and tEXr = tEXf = 10 ns, clock cycle

time = 120 ns; therefore, maximum operating frequency = 8.3 MHz)

tEXH

tEXL

tEXr

tEXf

VCC × 0.5

EXTAL

Figure 16.6 External Clock Input Timing

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