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H8S/2214 Scheda tecnica(PDF) 668 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 668 Page - Renesas Technology Corp |
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668 / 936 page ![]() Section 16 Clock Pulse Generator Rev.4.00 Sep. 18, 2008 Page 608 of 872 REJ09B0189-0400 Bit 3 RFCUT Description 0 System clock oscillator’s on-chip feedback resistor and duty adjustment circuit are used (Initial value) 1 System clock oscillator’s on-chip feedback resistor and duty adjustment circuit are not used Bit 2—Reserved: This bit can be read or written to, but should only be written with 0. Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit incorporated into the evaluation chip. The specified frequency multiplication factor is valid after a transition to software standby mode. With the LSI, STC1 and STC0 must both be set to 1. After a reset, STC1 and STC0 are both cleared to 0, and so must be set to 1. Bit 1 Bit 0 STC1 STC0 Description 0 0 ×1 (Initial value) 1 ×2 (Setting prohibited) 1 0 ×4 (Setting prohibited) 1 PLL is bypassed |
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