H8SSLASH2214 datasheet(680/936 Pages) RENESAS

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Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 620 of 872

REJ09B0189-0400

17.1.1

The power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and

MSTPCR registers. Table 17.2 summarizes these registers.

Table 17.2

Power-Down Mode Registers

Name

Abbreviation

R/W

Initial Value

Address*

Standby control register

SBYCR

R/W

H'08

H'FDE4

System clock control register

SCKCR

R/W

H'00

H'FDE6

Module stop control register

MSTPCRA

R/W

H'3F

H'FDE8

MSTPCRB

R/W

H'FF

H'FDE9

MSTPCRC

R/W

H'FF

H'FDEA

Note: * Lower 16 bits of the address.

17.2

17.2.1

Standby Control Register (SBYCR)

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

OPE

R/W

—

Bit

Initial value :

R/W

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. The SSBY

setting is not changed by a mode transition due to an interrupt, etc.

Bit 7

SSBY

Description

Transition to sleep mode after execution of SLEEP instruction

(Initial value)

Transition to subsleep mode after execution of SLEEP instruction in subactive mode

Transition to software standby mode after execution of SLEEP instruction

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