H8SSLASH2214 datasheet(713/936 Pages) RENESAS

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Section 18 Electrical Characteristics

Rev.4.00 Sep. 18, 2008 Page 653 of 872

REJ09B0189-0400

18.4.4

Timing of On-Chip Supporting Modules

Table 18.9 lists the timing of on-chip supporting modules.

Table 18.9

Timing of On-Chip Supporting Modules

Condition:

CC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,

φ = 2 to 16 MHz, T

a = –20°C to +75°C (regular specifications),

a = –40°C to +85°C (wide-range specifications)

Item

Symbol

Min.

Max.

Unit.

Test Conditions

I/O port Output data delay time

PWD

—

100

Figure 18.12

Input data setup time

PRS

—

Input data hold time

PRH

—

TPU

Timer output delay time

TOCD

—

100

Figure 18.13

Timer input setup time

TICS

—

Timer clock input setup time

TCKS

—

Figure 18.14

Single edge

TCKWH

1.5

—

cyc

Timer clock

pulse width

Both edges

TCKWL

2.5

—

SCI

Asynchronous

Scyc

—

cyc

Figure 18.15

Input clock

cycle

Synchronous

—

Input clock pulse width

SCKW

0.4

0.6

Scyc

Input clock rise time

SCKr

—

1.5

cyc

Input clock fall time

SCKf

—

1.5

Transmit data delay time

TXD

—

100

Figure 18.16

Receive data setup time

(synchronous)

RXS

—

Receive data hold time

(synchronous)

RXH

—

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