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H8S/2214 Scheda tecnica(PDF) 716 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 716 Page - Renesas Technology Corp |
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716 / 936 page ![]() Section 18 Electrical Characteristics Rev.4.00 Sep. 18, 2008 Page 656 of 872 REJ09B0189-0400 18.4.5 DMAC Timing Table 18.10 lists the DMAC timing. Table 18.10 DMAC Timing Condition: V CC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V, φ = 2 to 16 MHz, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions DREQ setup time t DRQS 40 — ns Figure 18.18 DREQ hold time t DRQH 10 — DREQ delay time t TED — 50 Figure 18.17 φ tTED TEND T1 T2 or T3 tTED Figure 18.17 DMAC TEND Output Timing φ tDRQS tDRQH DREQ Figure 18.18 DMAC DREQ Output Timing |
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