H8SSLASH2214 datasheet(825/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 765 of 872

REJ09B0189-0400

TSTR—Timer Start Register

H'FEB0

TPU

—

CST0

R/W

CST2

R/W

CST1

R/W

Bit

Initial value

R/W

Counter Start 2 to 0

TCNTn count operation is stopped

TCNTn performs count operation

(n = 2 to 0)

Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter

stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit

is cleared to 0, the pin output level will be changed to the set initial output value.

TSYR—Timer Synchro Register

H'FEB1

TPU

—

SYNC0

R/W

SYNC2

R/W

SYNC1

R/W

Bit

Initial value

R/W

Notes:

To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

Timer Synchro

TCNTn operates independently (TCNT presetting/clearing

is unrelated to other channels)

TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible

(n = 2 to 0)

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