H8SSLASH2214 datasheet(826/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 766 of 872

REJ09B0189-0400

IPRA —Interrupt Priority Register A

IPRB —Interrupt Priority Register B

IPRC —Interrupt Priority Register C

IPRD —Interrupt Priority Register D

IPRF —Interrupt Priority Register F

IPRG —Interrupt Priority Register G

IPRJ —Interrupt Priority Register J

IPRK —Interrupt Priority Register K

IPRM —Interrupt Priority Register M

H'FEC0

H'FEC1

H'FEC2

H'FEC3

H'FEC5

H'FEC6

H'FEC9

H'FECA

H'FECC

Interrupt Controller

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Bit

Initial value

R/W

Correspondence between Interrupt Sources and IPR Settings

Note: * Reserved bits. These bits cannot be modified and are always

read as 1.

Set priority (levels 7 to 0) for interrupt sources

Bits

6 to 4

2 to 0

IPRA

IRQ0

IRQ1

IPRB

IRQ2, IRQ3

IRQ4, IRQ5

IPRC

IRQ6, IRQ7

DTC

IPRD

Watchdog timer 0

—*

IPRF

TPU channel 0

TPU channel 1

IPRG

TPU channel 2

—

IPRJ

DMAC

SCI channel 0

IPRK

SCI channel 1

SCI channel 2

IPRM

EXIRQ3 to EXIRQ0

EXIRQ7 to EXIRQ4

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