H8SSLASH2214 datasheet(923/936 Pages) RENESAS

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Appendix D Pin States

Rev.4.00 Sep. 18, 2008 Page 863 of 872

REJ09B0189-0400

Port Name

Pin Name

MCU

Operating

Mode

Power-

Reset

Manual

Reset

Hardware

Standby

Mode

Software

Standby Mode,

Watch Mode

Bus-

Released

State

Program Execution

State, Sleep Mode,

Subsleep Mode

4 to 6

keep

[WAITE = 0]

keep

[WAITE = 1]

[WAITE = 0]

keep

[WAITE = 1]

[WAITE = 0]

I/O port

[WAITE = 1]

WAIT

PF2/

WAIT

keep

I/O port

4 to 6

keep

[BRLE = 0]

keep

[BRLE = 1]

[BRLE = 0]

I/O port

[BRLE = 1]

BACK

PF1/

BACK

keep

I/O port

4 to 6

keep

[BRLE = 0]

keep

[BRLE = 1]

[BRLE = 0]

I/O port

[BRLE = 1]

BREQ

PF0/

BREQ/IREQ2

keep

I/O port

4, 5

keep

[DDR · OPE = 0]

[DDR · OPE = 1]

[DDR = 0]

Input port

[DDR = 1]

CS0

(In sleep mode and

subsleep mode: H)

PG4/

CS0

keep

I/O port

4 to 6

keep

[DDR · OPE = 0]

[DDR · OPE = 1]

[DDR = 0]

Input port

[DDR = 1]

CS1 to CS3

PG3/

CS1

PG2/

CS2

PG1/

CS3/IRQ7

keep

I/O port

PG0/

IRQ6

4 to 7

keep

I/O port

Legend:

High level

Low level

High impedance

keep:

Input port becomes high-impedance, output port retains state

DDR

Data direction register

OPE:

Output port enable

WAITE: Wait input enable

BRLE: Bus release enable

Note: * L in modes 4 and 5 (address output)

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