H8SSLASH2214 datasheet(925/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Rev.4.00 Sep. 18, 2008 Page 865 of 872

REJ09B0189-0400

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

E.1

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the

RES signal low at

least 10 states before the

STBY signal goes low, as shown below. RES must remain low until

STBY signal goes low (delay from STBY low to RES high: 0 ns or more).

STBY

RES

t2 ≥ 0 ns

t1 ≥ 10 tcyc

Figure E.1 Timing of Transition to Hardware Standby Mode

(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do

not need to be retained,

RES does not have to be driven low as in (1).

E.2

Timing of Recovery from Hardware Standby Mode

Drive the

RES signal low and the NMI signal high approximately 100 ns or more before STBY

goes high to execute a power-on reset.

STBY

RES

tOSC

≥ 100 ns

Figure E.2 Timing of Recovery from Hardware Standby Mode

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