H8SSLASH2214 datasheet(179/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 119 of 872

REJ09B0189-0400

Section 6 Bus Controller

6.1

Overview

The H8S/2214 Group has an on-chip bus controller (BSC) that manages the external address space

divided into eight areas. The bus specifications, such as bus width and number of access states,

can be set independently for each area, enabling multiple memories to be connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).

6.1.1

Features

The features of the bus controller are listed below.

• Manages external address space in area units

⎯ Manages the external space as 8 areas of 2-Mbytes

⎯ Bus specifications can be set independently for each area

⎯ Burst ROM interface can be set

• Basic bus interface

⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7

⎯ 8-bit access or 16-bit access can be selected for each area

⎯ 2-state access or 3-state access can be selected for each area

⎯ Program wait states can be inserted for each area

• Burst ROM interface

⎯ Burst ROM interface can be set for area 0

⎯ Choice of 1- or 2-state burst access

• Idle cycle insertion

⎯ An idle cycle can be inserted in case of an external read cycle between different areas

⎯ An idle cycle can be inserted in case of an external write cycle immediately after an

external read cycle

• Bus arbitration function

⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC

• Other features

⎯ External bus release function

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