H8SSLASH2214 datasheet(175/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 115 of 872

REJ09B0189-0400

5.5.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1:

EEPMOV.W

MOV.W

R4,R4

BNE

5.5.5

IRQ Interrupts

When operating from a clock signal, interrupt requests are accepted in synchronization with the

clock.

Interrupt requests are accepted asynchronously in software standby mode.

See section 18.4.2, Control Signal Timing, for the input conditions.

5.5.6

NMI Interrupt Usage Notes

The NMI interrupt invokes exception handling that is performed by cooperation between the

interrupt controller and the CPU built into this IC during normal operation under the conditions

stipulated in the electrical characteristics. No operations, including the NMI interrupt, are

guaranteed if there are abnormal inputs to the IC pins or if there are software problems (e.g. if the

application has crashed or gone into an infinite loop). In such cases, the IC can be returned to the

normal program execution state by applying an external reset.

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