H8SSLASH2214 datasheet(191/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 131 of 872

REJ09B0189-0400

6.2.5

Bus Control Register L (BCRL)

BRLE

R/W

—

R/W

—

R/W

—

R/W

WAITE

R/W

—

R/W

—

R/W

Bit

Initial value

R/W

BCRL is an 8-bit readable/writable register that performs selection of the external bus-released

state protocol, and enabling or disabling of

WAIT pin input.

BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized

by a manual reset or in software standby mode.

Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.

Bit 7

BRLE

Description

External bus release is disabled.

BREQ and BACK can be used as I/O ports.

(Initial value)

External bus release is enabled.

Bit 6—Reserved: Only 0 should be written to this bit.

Bit 5—Reserved: This bit cannot be modified and is always read as 0.

Bit 4—Reserved: Only 0 should be written to this bit.

Bit 3—Reserved: Only 1 should be written to this bit.

Bits 2 and 1—Reserved: Only 0 should be written to these bits.

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the

WAIT

pin.

Bit 0

WAITE

Description

Wait input by

WAIT pin disabled. WAIT pin can be used as I/O port.

(Initial value)

Wait input by

WAIT pin enabled

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