H8SSLASH2214 datasheet(233/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 173 of 872

REJ09B0189-0400

Section 7 DMA Controller

7.1

Overview

The H8S/2214 Group has an on-chip DMA controller (DMAC) which can carry out data transfer

on up to 4 channels.

7.1.1

Features

The features of the DMAC are listed below.

• Choice of short address mode or full address mode

Short address mode

⎯ Maximum of 4 channels can be used

⎯ Choice of dual address mode

⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is

specified as 24 bits and the other as16 bits

⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode

Full address mode

⎯ Maximum of 2 channels can be used

⎯ Transfer source and transfer destination address specified as 24 bits

⎯ Choice of normal mode or block transfer mode

• 16-Mbyte address space can be specified directly

• Byte or word can be set as the transfer unit

• Activation sources: internal interrupt, external request, auto-request (depending on transfer

mode)

⎯ Three 16-bit timer-pulse unit (TPU) compare match/input capture interrupts

⎯ Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception

complete interrupt

⎯ External request

⎯ Auto-request

• Module stop mode can be set

⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by

setting module stop mode

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