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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2214 Scheda tecnica(PDF) 234 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 234 Page - Renesas Technology Corp |
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234 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 174 of 872 REJ09B0189-0400 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7.1. Internal address bus Address buffer Processor Internal interrupts TGI0A TGI1A TGI2A TXI0 RXI0 TXI1 RXI1 External pins DREQ0 DREQ1 TEND0 TEND1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMACR1B DMACR1A DMACR0B DMACR0A DMATCR DMABCR Data buffer Internal data bus MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Legend: DMA write enable register DMA terminal control register DMA band control register (for all channels) DMA control register Memory address register I/O address register Executive transfer counter register DMAWER: DMATCR: DMABCR: DMACR: MAR: IOAR: ETCR: Figure 7.1 Block Diagram of DMAC |
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