H8SSLASH2214 datasheet(249/936 Pages) RENESAS

249 / 936 page

Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 189 of 872

REJ09B0189-0400

Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B.

Bit 7

DTE1B

Description

Data transfer disabled

(Initial value)

Data transfer enabled

Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.

Bit 6

DTE1A

Description

Data transfer disabled

(Initial value)

Data transfer enabled

Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.

Bit 5

DTE0B

Description

Data transfer disabled

(Initial value)

Data transfer enabled

Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.

Bit 4

DTE0A

Description

Data transfer disabled

(Initial value)

Data transfer enabled

Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an

interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the

DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to

the CPU or DTC.

A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt

handling routine, or by performing processing to continue transfer by setting the transfer counter

and address register again, and then setting the DTE bit to 1.

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