H8SSLASH2214 datasheet(271/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 211 of 872

REJ09B0189-0400

(5) Block Transfer Mode

In response to a single transfer request, a block transfer of the specified block size is carried out.

This is repeated the specified number of times, once each time there is a transfer request. At the

end of each single block transfer, one address is restored to its original setting. An interrupt

request can be sent to the CPU or DTC when the specified number of block transfers have been

completed. Both addresses are specified as 24 bits.

7.5.2

Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,

MAR is updated after each byte or word transfer in response to a single transfer request, and this is

executed the number of times specified in ETCR.

One address is specified by MAR, and the other by IOAR. The transfer direction can be specified

by the DTDIR bit in DMACR.

Table 7.7 summarizes register functions in sequential mode.

Table 7.7

Function

DTDIR = 0 DTDIR = 1 Initial Setting

Operation

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Incremented/

decremented every

transfer

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCR

Transfer counter

Number of transfers Decremented every

transfer; transfer

ends when count

reaches H'0000

Legend:

MAR:

Memory address register

IOAR:

I/O address register

ETCR: Transfer count register

DTDIR: Data transfer direction bit

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred.

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