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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2214 Scheda tecnica(PDF) 272 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 272 Page - Renesas Technology Corp |
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272 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 212 of 872 REJ09B0189-0400 IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.3 illustrates operation in sequential mode. Address T Address B Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend: Address T = L Address B = L + (–1)DTID ⋅ (2DTSZ ⋅ (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. |
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