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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2214 Scheda tecnica(PDF) 292 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 292 Page - Renesas Technology Corp |
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292 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 232 of 872 REJ09B0189-0400 7.5.8 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. φ Address bus DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3 T1 T2 T3 T1 T2 Figure 7.15 Example of DMA Transfer Bus Timing |
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