H8SSLASH2214 datasheet(293/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 233 of 872

REJ09B0189-0400

7.5.9

DMAC Bus Cycles (Dual Address Mode)

(1) Short Address Mode

Figure 7.16 shows a transfer example in which

TEND output is enabled and byte-size short

address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state

access space to internal I/O space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release

Last transfer

cycle

DMA

write

DMA

dead

DMA

read

DMA

write

DMA

read

DMA

write

Bus release

Bus

release

Figure 7.16 Example of Short Address Mode Transfer

A one-byte or one-word transfer is performed for one transfer request, and after the transfer the

bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when

TEND output is enabled, TEND output goes low in the transfer cycle in

which the transfer counter reaches 0.

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