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H8S/2214 Scheda tecnica(PDF) 301 Page - Renesas Technology Corp

Il numero della parte H8S/2214
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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Section 7 DMA Controller
Rev.4.00 Sep. 18, 2008 Page 241 of 872
REJ09B0189-0400
Table 7.13
DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1
Channel 1B
Low
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.24 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA write
DMA
read
φ
Address bus
RD
HWR
LWR
DMA control
Channel 0A
Channel 0B
Channel 1
Idle
Write
Idle
Read
Write
Idle
Read
Write
Read
Request clear
Request
hold
Request
hold
Request clear
Request clear
Bus
release
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Channel 1 transfer
Bus
release
Request
hold
Read
Selection
Non-
selection
Selection
Figure 7.24 Example of Multi-Channel Transfer



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