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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2214 Scheda tecnica(PDF) 302 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 302 Page - Renesas Technology Corp |
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302 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 242 of 872 REJ09B0189-0400 7.5.11 Relation between the DMAC, External Bus Requests, and the DTC There can be no break between a DMA cycle read and a DMA cycle write. This means that an external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, an external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as external bus release. However, simultaneous operation may not be possible when a write buffer is used. |
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