H8SSLASH2214 datasheet(318/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 258 of 872

REJ09B0189-0400

8.2.5

DTC Transfer Count Register A (CRA)

76543210

CRAH

CRAL

Bit

Initial value

—

Unde-

fined

R/W

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)

and the lower 8 bits (CRAL). In repeat mode, CRAH holds the transfer count and CRAL functions

as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size and

functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is

transferred and when the counter value becomes H'00 the contents of CRAH are transferred. This

operation is repeated.

8.2.6

DTC Transfer Count Register B (CRB)

76543210

Bit

Initial value

—

——

—

——

—

——

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

R/W

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

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