H8SSLASH2224 datasheet(371/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 285 of 982

REJ09B0054-0500

9.2.2

DTC Mode Register B (MRB)

MRB is an 8-bit register that selects the DTC operating mode.

Bit

Bit Name

Initial Value

R/W

Description

CHNE

Undefined



DTC Chain Transfer Enable

This bit specifies a chain transfer. For details, refer

to section 9.5.4, Chain Transfer.

In data transfer with CHNE set to 1, determination of

the end of the specified number of transfers,

clearing of the interrupt source flag, and clearing of

DTCER, are not performed.

0: DTC data transfer completed (waiting for start)

1: DTC chain transfer (reads new register

information and transfers data)

DISEL

Undefined



DTC Interrupt Select

This bit specifies whether CPU interrupt is disabled

or enabled after a data transfer.

0: Interrupt request is issued to the CPU when the

specified data transfer is completed

1: DTC issues interrupt request to the CPU in every

data transfer (DTC does not clear the interrupt

request flag that is a cause of the activation)

5 to



Undefined



Reserved

These bits have no effect on DTC operation. The

write value should always be 0.

9.2.3

DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

9.2.4

DTC Destination Address Register (DAR)

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

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