H8SSLASH2224 datasheet(374/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 288 of 982

REJ09B0054-0500

9.2.8

DTC Vector Register (DTVECR)

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

Bit

Bit Name

Initial

Value

R/W

Description

SWDTE

R/W

DTC Software Activation Enable

Enables or disables the DTC software activation.

0: Disables the DTC software activation.

1: Enables the DTC software activation.

[Clearing conditions]

• When the DISEL bit is 0 and the specified

number of transfers have not ended

• When 0 is written to the DISEL bit after a

software-activated data transfer end interrupt

(SWDTEND) request has been sent to the CPU.

[Retaining conditions]

• When the DISEL bit is 1 and data transfer has

ended

• When the specified number of transfers have

ended

• When the software-activated data transfer is in

process

DTVEC6

DTVEC5

DTVEC4

DTVEC3

DTVEC2

DTVEC1

DTVEC0

R/W

DTC Software Activation Vectors 0 to 6

These bits specify a vector number for DTC

software activation.

The vector address is expressed as H'0400 +

(vector number

× 2). For example, when DTVEC6 to

DTVEC0 = H'10, the vector address is H'0420.

These bits are writable when SWDTE = 0.

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